Avionics systems have become a significant feature in all aerospace systems and, in many cases, the avionics predominates in the total system. As the state of the art is advanced and implemented, the complexity and circuit density factor of the avionics is increased geometrically.
The ability to identify and repair or replace failed components in these complex avionics systems correlates directly to the success of the avionics systems. No matter how elegant, well designed, and functional a system is, if it is not kept in working order, it will be of no practical use. Automatic test equipment has the most promise in being able to handle the variety and complexity of present and future avionics in a timely manner.
There are two basic ways to isolate logic failures within a digital circuit, fault signature isolation and probed fault isolation. The general difference is that the fault signature approach uses data available on the circuit output pins to determine the location of a fault, and the probed fault isolation approach uses data on the component pins. The primary difference between the two approaches is in the assumptions made. Specifically, that for a fault dictionary, each failure that is to be isolated must be characterized and simulated, whereas in a proble isolation approach, all failures that affect the logic function of a circuit will be isolated because only the normal function of the circuit need be characterized.
In order to utilize automatic test equipment, two areas of understanding are required: the normal operation of the circuit in order to determine whether or not the circuit is functioning; and the ways in which the circuit can fail in order to identify the location of the failure. Due to the complexity of most modern avionics, there is too much detail of operation in most circuit functions to be determined by manual means. A good computer-aided program preparation system does the drudgerous, time-consuming work of simulating the detail functions of a circuit and provides information about circuit activities to the analyst so that the test can be developed.
Typically, the development costs of a probe-isolated test is less than for an equivalent fault dictionary test, because the analyst need not run a fault simulation for each fault, and the model of the circuit need not include all of the fault-mode representations of the circuit. Because these two items do not have to be dealt with, the calendar time required for test program development is reduced.
There are several automatic test systems presently in use, as for example, the Hybrid Automatic Test System (HATS), manufactured by General Dynamics Corp. In this system, a model of the circuit board to be tested (called a LASAR model) is generated from circuit schematics and the like. In the system process, an equivalent NAND model of the circuit is generated, and node numbers are assigned to the various nodes. A pattern set is then generated by applying voltages to the circuit input pins and ascertaining the voltages on the output pins. The patterns are generated by reapplying different combinations of input voltages, getting the different output voltages. Each combination is a pattern set. This operation is carried out sequentially to establish a complete pattern set. In effect, an attempt is made to exercise everything in the circuit, and that is reflected on the output nodes. When a node is probed, HATS, utilizing a computer, automatically determines if the node is in the state is should be in, and checks the voltages on all nodes.
The problem, however, with library types of detection systems, lies in the frequent existence of ambiguity groups. As an example, using output pins on a unit under test to determine faults, and assuming five hundred or more patterns tested, it would not be unusual to find as many as ten or more incorrect outputs, that is, certain pin combinations that have the wrong voltages on them. In these circumstances, the HATS goes to the library, where a match of failure patterns may include as many as ten or more different nodes. The tester or technician thus may have to change many parts on the circuit board.
Stated another way, one of the primary areas of difficulty in prior art automatic test systems is that of signal loops in the circuit. A signal loop manifests itself when a failure occurs in a circuit in such a way as to cause both the inputs and outputs of several components to show erroneous states simultaneously, all the components arranged topologically in a loop structure. The problem is then to identify where in the loop the failure actually occurred.
Ambiguity of failure location within the loop causes components that have no failure to be replaced, which utilizes unnecessary manpower, spares, and runs a high risk of circuit board damage.
One approach to circuit testing has been the use of manually operated logic probes, such as the Hewlett-Packard Model 10525T Logic Probe. This probe detects and indicates valid logic levels, the presence and polarity of single pulses of 10 nanoseconds or greater in duration, and intermediate or "BAD" logic levels, such as an open input on a TTL (transistor transistor logic) gate or an open circuit, etc. The probe includes a logic level indicator lamp at the probe tip which gives the user an immediate indication of the logic states in the circuit under test. The lamp normally shines dim, and is driven to bright for inputs above a rough logic one threshold and to off for inputs below a rough logic zero threshold. At voltage levels between the logic one and zero thresholds, and for open circuits, the lamp remains dim. The lamp will flash on and off at about ten times per second for pulse train inputs greater than about 10 H.sub.z. The logic probe suffers from several disadvantages. Power supply potentials more positive than plus seven volts or more negative than minus fifteen volts will cause probe damage. The probe works on only one logic family, namely, TTL, and does not clearly identify and differentiate when it is in a forbidden zone of voltage. Additionally, the probe does not differentiate and distinguish between different types of pulses, for example, square wave pulses. Finally, the logic probe is not adapted to be readily usable with an automatic test system.
A more efficient, flexible and utilizable guided logic probe is disclosed in copending U.S. Patent Application Ser. No. 191,048, filed Sept. 25, 1980, for "Guided-Logic Probe", assigned to the assignees herein. The application discloses an improved guided-logic probe which performs greatly improved manual testing functions, but also deals with inclusion in the probe of suitable circuitry that make it readily adaptable to function in conjunction with the computer of an automatic test system, as for example the computer used in the HATS. The disclosure of the aforementioned copending application is hereby incorporated by reference. While the probe is of improved design for use both manually and/or in conjunction with an automatic test system, it nevertheless is not an automatic system and cannot, in and of itself, solve the fault ambiguity problems discussed hereinabove.
In view of the problems associated with the aforementioned prior art approaches, there is a need to develop an efficient system and apparatus for testing circuits and locating and identifying faulty components therein.
From the foregoing, it can be seen that it is a primary object of the present invention to provide a novel test system and process for testing circuits, and for identifying and locating faulty components therein.
It is a further object of this invention to provide a novel test system and process which can readily locate and identify a faulty signal loop within a circuit, and which can then identify the component or components within the loop which actually failed.
It is another object of this invention to provide a novel automatic guided-probe system which works in conjunction with existing automatic test equipment and systems.
It is yet another object of the present invention to provide a digital-fault loop probe and system which provides improved resolution in identifying a smaller segment for the probable cause of failure in a circuit than existing test systems, and a more reliable indication of the cause of failure.
It is a further object of the present invention to provide a process and system for converting an existing dynamic automatic test system into a dynamic automatic test system tht will perform guided-probe fault isolation and reduce the possibility of ambiguity of failure location as a result of failure within a circuit signal loop.